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1. general description the hef4081b is a quad 2-input and gate. the outputs are fully buffered for highest noise immunity and pattern insensitiv ity to output impedance variations. it operates over a recommended v dd power supply range of 3 v to 15 v referenced to v ss (usually ground). unused inputs must be connected to v dd , v ss , or another input. the hef4081b is suitable for use over both the industrial ( ? 40 c to +85 c) and automotive ( ? 40 c to +125 c) temperature ranges. 2. features ? fully static operation ? 5 v, 10 v, and 15 v parametric ratings ? standardized symmetrical output characteristics ? inputs and outputs are protected against electrostatic effects ? operates across the automotive temperature range from ? 40 c to +125 c ? complies with jedec standard jesd 13-b 3. ordering information hef4081b quad 2-input and gate rev. 06 ? 2 december 2009 product data sheet table 1. ordering information all types operate from ? 40 c to +125 c. type number package name description version hef4081bp dip14 plastic dual in-line package; 14 leads (300 mil) sot27-1 HEF4081BT so14 plastic small outline pa ckage; 14 leads; body width 3.9 mm sot108-1
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 2 of 11 nxp semiconductors hef4081b quad 2-input and gate 4. functional diagram 5. pinning information 5.1 pinning 5.2 pin description fig 1. functional diagram fig 2. logic diagram (one gate) 001aai139 1a 1b 1y 2 1 3 2a 2b 2y 6 5 4 3a 3b 3y 9 8 10 4a 4b 4y 13 12 11 001aag18 0 na nb ny fig 3. pin configuration hef4081b 1a v dd 1b 4b 1y 4a 2y 4y 2a 3y 2b 3b v ss 3a 001aag178 1 2 3 4 5 6 7 8 10 9 12 11 14 13 table 2. pin description symbol pin description 1a to 4a 1, 5, 8, 12 input 1b to 4b 2, 6, 9, 13 input 1y to 4y 3, 4, 10, 11 output v ss 7 ground (0 v) v dd 14 supply voltage
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 3 of 11 nxp semiconductors hef4081b quad 2-input and gate 6. functional description [1] h = high voltage level; l = low voltage level. 7. limiting values [1] for dip14 packages: above t amb = 70 c, p tot derates linearly with 12 mw/k. [2] for so14 packages: above t amb = 70 c, p tot derates linearly with 8 mw/k. 8. recommended operating conditions table 3. function table [1] input output na nb ny lll lhl hl l hhh table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to v ss = 0 v (ground). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +18 v i ik input clamping current v i < -0.5 v or v i >v dd + 0.5 v - 10 ma v i input voltage ? 0.5 v dd + 0.5 v i ok output clamping current v o <-0.5v or v o >v dd + 0.5 v - 10 ma i i/o input/output current - 10 ma i dd supply current - 50 ma t stg storage temperature ? 65 +150 c t amb ambient temperature ? 40 +125 c p tot total power dissipation t amb = ? 40 c to + 125 c dip14 [1] -750mw so14 [2] -500mw p power dissipation per output - 100 mw table 5. recommended operating conditions symbol parameter conditions min max unit v dd supply voltage 3 15 v v i input voltage 0 v dd v t amb ambient temperature in free air ? 40 +125 c t/ v input transition rise and fall rate v dd = 5 v - 3.75 s/v v dd = 10 v - 0.5 s/v v dd = 15 v - 0.08 s/v
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 4 of 11 nxp semiconductors hef4081b quad 2-input and gate 9. static characteristics table 6. static characteristics v ss = 0 v; v i =v ss or v dd ; unless otherwise specified. symbol parameter conditions v dd t amb = ? 40 c t amb = +25 c t amb = +85 c t amb = +125 c unit min max min max min max min max v ih high-level input voltage | i o | < 1 a 5 v 3.5 - 3.5 - 3.5 - 3.5 - v 10 v 7.0 - 7.0 - 7.0 - 7.0 - v 15 v 11.0 - 11.0 - 11.0 - 11.0 - v v il low-level input voltage | i o | < 1 a 5 v - 1.5 - 1.5 - 1.5 - 1.5 v 10 v - 3.0 - 3.0 - 3.0 - 3.0 v 15 v - 4.0 - 4.0 - 4.0 - 4.0 v v oh high-level output voltage | i o | < 1 a 5 v 4.95 - 4.95 - 4.95 - 4.95 - v 10 v 9.95 - 9.95 - 9.95 - 9.95 - v 15 v 14.95 - 14.95 - 14.95 - 14.95 - v v ol low-level output voltage | i o | < 1 a 5 v - 0.05 - 0.05 - 0.05 - 0.05 v 10 v - 0.05 - 0.05 - 0.05 - 0.05 v 15 v - 0.05 - 0.05 - 0.05 - 0.05 v i oh high-level output current v o = 2.5 v 5 v ? 1.7 - ? 1.4 - ? 1.1 - ? 1.1 - ma v o = 4.6 v 5 v ? 0.64 - ? 0.5 - ? 0.36 - ? 0.36 - ma v o = 9.5 v 10 v ? 1.6 - ? 1.3 - ? 0.9 - ? 0.9 - ma v o = 13.5 v 15 v ? 4.2 - ? 3.4 - ? 2.4 - ? 2.4 - ma i ol low-level output current v o = 0.4 v 5 v 0.64 - 0.5 - 0.36 - 0.36 - ma v o = 0.5 v 10 v 1.6 - 1.3 - 0.9 - 0.9 - ma v o = 1.5 v 15 v 4.2 - 3.4 - 2.4 - 2.4 - ma i i input leakage current 15 v - 0.1 - 0.1 - 1.0 - 1.0 a i dd supply current all valid input combinations; i o =0a 5 v - 0.25 - 0.25 - 7.5 - 7.5 a 10 v - 0.5 - 0.5 - 15.0 - 15.0 a 15 v - 1.0 - 1.0 - 30.0 - 30.0 a c i input capacitance ---7.5-- - -pf
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 5 of 11 nxp semiconductors hef4081b quad 2-input and gate 10. dynamic characteristics [1] the typical value of the propagation delay and output transi tion time can be calculated with the extrapolation formula (c l in pf). table 7. dynamic characteristics t amb = 25 c; for waveforms see figure 4 ; for test circuit see figure 5 ; unless otherwise specified. [1] symbol parameter conditions v dd extrapolation formula min typ max unit t phl high to low propagation delay na or nb to ny 5 v 28 ns + (0.55 ns/pf)c l - 55 110 ns 10 v 14 ns + (0.23 ns/pf)c l -25 50 ns 15 v 12 ns + (0.16 ns/pf)c l -20 40 ns t plh low to high propagation delay na or nb to ny 5 v 18 ns + (0.55 ns/pf)c l -45 90 ns 10 v 9 ns + (0.23 ns/pf)c l -20 40 ns 15 v 7 ns + (0.16 ns/pf)c l -15 30 ns t thl high to low output transition time 5 v 10 ns + (1.0 ns/pf)c l - 60 120 ns 10 v 9 ns + (0.42 ns/pf)c l -30 60 ns 15 v 6 ns + (0.28 ns/pf)c l -20 40 ns t tlh low to high output transition time 5 v 10 ns + (1.00 ns/pf)c l - 60 120 ns 10 v 9 ns + (0.42 ns/pf)c l -30 60 ns 15 v 6 ns + (0.28 ns/pf)c l -20 40 ns table 8. dynamic power dissipation v ss = 0 v; t r = t f 20 ns; t amb = 25 c. symbol parameter v dd typical formula where: p d dynamic power dissipation 5 v p d = 450 f i + (f o c l ) v dd 2 ( w) f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; (f o c l ) = sum of the outputs; v dd = supply voltage in v. 10 v p d = 2900 f i + (f o c l ) v dd 2 ( w) 15 v p d = 11700 f i + (f o c l ) v dd 2 ( w)
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 6 of 11 nxp semiconductors hef4081b quad 2-input and gate 11. waveforms measurement points are given in table 9 . logic levels: v ol and v oh are typical output voltage levels that occur with the output load. fig 4. input to output propagation delay and output transition times 001aai14 0 na, nb input ny output t phl t plh 0 v v i v m v m v oh v ol t thl t tlh 90 % 10 % 10 % 90 % t r t f table 9. measurement points supply voltage input output v dd v m v m 5 v to 15 v 0.5v dd 0.5v dd test data is given in table 10 . definitions for test circuit: dut = device under test. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 5. test circuit v dd v i v o 001aag18 2 dut c l r t g table 10. test data supply voltage input load v dd v i t r , t f c l 5 v to 15 v v ss or v dd 20 ns 50 pf
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 7 of 11 nxp semiconductors hef4081b quad 2-input and gate 12. package outline fig 6. package outline sot27-1 (dip14) unit a max. 1 2 (1) (1) b 1 cd (1) z ee m h l references outline version european projection issue date iec jedec jeita mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot27-1 99-12-27 03-02-13 a min. a max. b max. w m e e 1 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 2.2 4.2 0.51 3.2 0.068 0.044 0.021 0.015 0.77 0.73 0.014 0.009 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.087 0.17 0.02 0.13 050g04 mo-001 sc-501-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 14 1 8 7 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. d ip14: plastic dual in-line package; 14 leads (300 mil) sot27 -1
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 8 of 11 nxp semiconductors hef4081b quad 2-input and gate fig 7. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale s o14: plastic small outline package; 14 leads; body width 3.9 mm sot108 -1
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 9 of 11 nxp semiconductors hef4081b quad 2-input and gate 13. revision history table 11. revision history document id release date data sheet status change notice supersedes hef4081b_6 20091202 product data sheet - hef4081b_5 modifications: ? section 8 ? recommended operating conditions ? , t/ v values updated. hef4081b_5 20090629 product data sheet - hef4081b_4 hef4081b_4 20080526 product data sheet - hef4081b_cnv_3 hef4081b_cnv_3 19950101 product specification - hef4081b_cnv_2 hef4081b_cnv_2 19950101 pr oduct specification - -
hef4081b_6 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 06 ? 2 december 2009 10 of 11 nxp semiconductors hef4081b quad 2-input and gate 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
nxp semiconductors hef4081b quad 2-input and gate ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 2 december 2009 document identifier: hef4081b_6 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 functional description . . . . . . . . . . . . . . . . . . . 3 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 recommended operating conditions. . . . . . . . 3 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 4 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 legal information. . . . . . . . . . . . . . . . . . . . . . . 10 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 14.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 15 contact information. . . . . . . . . . . . . . . . . . . . . 10 16 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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